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Скиллы

FPGA
Verilog
System Verilog
Matlab
Radiolocation
Wireless
VHDL
Tcl
C / C++
Xilinx
Git
Agile
Scrum
SAFe
RFSoC
Versal
PCIe

Опыт работы

Senior FPGA Developer
с 08.2025 - По настоящий момент |Novye Telekom Resheniya (NTR)
FPGA, Verilog, System Verilog, Matlab, Wireless, RFSoC, Versal
● Development and verification of FPGA IP cores in the wireless domain. ● Vitis Accelerator Flow. ● HW signal analysis. ● Development of projects with Xilinx RFSoC and Versal.
Head of Software Development Department
10.2006 - 08.2025 |TsKBA
FPGA, Verilog, System Verilog, Matlab, Raiolocation
● Development of FPGA, SoC, and target software architecture for civil and military radar systems. ● Participation in the development of information processing units during the schematic design coordination stage. ● Development of digital signal processing and radar algorithms. ● Implementation of DSP and radar algorithms in FPGA and SoC. ● Work with SDR. ● Development of synchronization systems. ● Development of the logical part of the Serial RapidIO interface. ● Development and implementation of active transponder algorithms. ● Implementation of FPGA algorithms for meteorological radars. ● Development and implementation of active interference compensation algorithms. ● Development of system software for power-up and status monitoring of information processing unit hardware.

Образование

Specialist (Магистр)
2003 - 2009
Tula State University, Faculty of Cybernetics, Radiophysics and Electronics

Языки

РусскийРоднойАнглийскийСреднийИтальянскийБазовый