● Developed firmware in C for wireline logging embedded system in extreme thermal environments (>150°C), optimizing reliability and stability under harsh constraints while reducing tool failure rates to 0.106%. ● Engineered FreeRTOS on dsPIC33E for deterministic task scheduling in real-time downhole operations; integrated multi-sensor acquisition (RTD, gyro/accelerometer, acoustic) and FPGA interfacing for robust telemetry. ● Architected FPGA acquisition pipeline in Verilog, including high-throughput ADC sampling and signal processing of acoustic piezo arrays; implemented a custom frame-sync protocol to bridge MCU–FPGA communication. ● Developed and validated analog frontend (signal conditioning, power supply) and digital comms (SPI, I2C), performing low-level debugging with oscilloscopes to ensure reliable hardware bring-up. ● Implemented CAN bus for packaging and transmitting aggregated sensor and FPGA data to the Wireline Telemetry System, while supporting LIN protocol for diagnostics and telemetry configuration.

● Managed and instructed laboratory sessions for over 60 undergraduate students in Circuit Analysis.

● Developed PHY RTL for high-speed proprietary IP (USB/PCIe), enabling efficient ATE testing and pre-silicon SoC diagnosis. ● Automated ATPG pattern generation and optimized conversion to HSIO packets, enhancing test efficiency with TestMAX ALE. ● Streamlined JTAG TAP-based testing, significantly reducing GPIO requirements and enhancing SoC validation effectiveness. ● Built and optimized testbenches for AXI/SCAN loopback tests, strengthening RTL verification processes.

● Awarded a full research scholarship: proposed a framework to enhance the security of Cyber-Physical Systems (CPS), advocating for FPGA encryption enhancements. ● Shared the impactful findings with ACM Computer Survey Journal. Research Projects: 1. Hardware implementation of symmetric cryptography (thesis). Spring 2022 – Fall 2023. ● Implemented and optimized AES cryptographic variants on Artix-7 FPGA, achieving 5× throughput gains and exploring silicon PPA trade-offs. Verified designs using Xilinx tools, RTL (VHDL), and TCL scripting. 2. SenseBall – A silo monitoring system (senior design project). Spring 2019. ● Designed a robust wireless sensor network for silo monitoring using a PIC24 microcontroller, integrating acoustic and CO2 sensors for precise environmental data capture with efficient IO, clocking, and voltage control. ● Enhanced computational efficiency by 10% via memory-efficient Fourier transform implementation in Embedded C, enabling long-range (8-mile) LoRaWAN transmission with MiWi and IoT analytics integration through an Android app.

● Achieved EAL 6+ certification for OPOLO Hardware Wallet by developing secure C firmware with AES-CMAC encryption on STM32 and implementing interface layers for Android and JavaScript Desktop App to enable authentic data exchange. ● Designed and implemented Password Manager/Mnemonics-Backup on RFID cards with efficient flash memory management, earning recognition in Forbes' 10 Most Cutting Edge Wallets of 2020. ● Enhanced UX and security by optimizing touchscreen drivers, integrating secure elements, and improving memory management for the ARM Cortex M4 platform.