1. Project: Google-Verification of FPGA-Taara. This project involves verification of multiple blocks within FPGA-Taara. ● Test plan development. ● Developed sequences for peripherals, clock and reset block. ● Regression feature update. 2. Project: Intel-Verification of SoC-Ethernet peripherals. This project involves verification of SoC-Tensilica for Ethernet frame transfer containing multiple Subsystem and a mini SoC which involves uvm environment and C-based test. ● Verification of multiple slave peripheral blocks interacting with master. ● Test plan development. ● Developed sequences for peripherals access and data integrity. ● Regression enhancement in existing test bench. ● Functional coverage model integration and analysis. ● Setup regression environment.

Project: Ciena-Verification of multiple sub system blocks in FPGA. This project involves verification of multiple sub system blocks i.e. power sequence of BMC, Main Board, CPU, register map, remote upgrade. LED frame check. ● Verification of multiple blocks communicating within main board. ● Test plan development. ● Test bench development. ● Developed sequences for power up, interrupt and miscellaneous. ● Code/toggle coverage analysis. ● Functional specification development. ● Automated regression execution.

Project: Ciena- Verification of Avalon Interface. This project involves verification of streaming interface of Avalon. ● Verification using SV/UVM. ● Responsible for test plan development. ● Developed sequences for driver, monitor, scoreboard and miscellaneous.

1. Project: NEC-System MCU (Memory Control Unit) Verification. This Project involves C-based testcase, integration verification of multiple blocks with code and functional coverage analysis. ● Verification of sub blocks communication with MCU. ● Assertion check. ● Code and functional coverage analysis. ● Test case development. 2. Project: NEC-System Simulation Model Verification. The Project involves verification of NoC simulation model. ● Verification of Pseudo NOC model. ● Simulation run and debug. ● Sequence development. ● Automation with python scripting for simulation results.

● Responsible for providing training for verilog,system verilog,uvm and fifo project ODC.

Project: Renesas-Design Verification of SYS Register Model. The Project involves design and verification of SYS Register Model. ● Designing environment using Verilog. ● Connectivity check of design by lint. ● Hardware specification development. ● Dynamic verification with simulation tool.