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  4. Senior IP Design Engineer

Senior IP Design Engineer

Оплата: По договоренности
Удаленно
Full-time
Постоянная работа
FPGA PCI DSS Verilog Ethernet 802.1Q

A company that develops modern CPUs, GPUs, and architectures for data centers, gaming systems, and AI workloads is seeking a specialist for the position of Design Verification Engineer is looking for Senior IP Design Engineer.


Responsibilities:


Design high-performance IP targeting FPGA/Adaptive SoC technology using SystemVerilog RTL. Deliver synthesis-ready designs meeting timing and integration requirements.


Key Skills:


  • Knowledge and work experience with SystemVerilog RTL design
  • 100Gb Ethernet, PCIe Gen5, AMBA/AXI
  • Deep understanding of FPGA/Adaptive SoC design flow including P&R and timing closure
  • Knowledge and work experience with Vivado/Vitis expertise
  • Knowledge and work experience with Python/Tcl scripting
  • Git & CI/CD experience